In Double Data Rate Fourth Generation (DDR4) memory technologies, different settings might be required for different dynamic random-access memories (DRAMs) on a given bus. For example, different signal integrity settings have to be set via per-DRAM addressability (PDA) or per-buffer addressability (PBA). The signal integrity setting may be set to avoid data erroneously flipping or glitches on a bus.
Currently, shadow registers are used to store a mode register set (MRS) command that was written to a DRAM on a per memory rank basis. A memory rank is a set of DRAM microchips connected to the same chip select. For PDA and PBA, per memory rank storage of MRS commands causes only one value to be stored across an entire memory rank. For instance, only a last value sent to a rank (and not the prior 19 values) will be stored. The storage of only one value across an entire rank leads to a loss of information in the shadow registers. For example, the settings used for a DRAM can be indeterminable. The loss of information creates problems for automatic routines that write-back settings into DRAMs. For instance, software based training schemes may be required to assist the routines. The software based training schemes require additional code and processing time.